Analog-to-digital converters (ADCs) are used in a wide range of signal processing applications and are available in a variety of implementations. Because practical ADCs cannot perform instantaneous conversion, a device known as a sample-and-hold (SH) circuit is often used to sample an analog input signal and hold the signal at a constant value for a specified time period, during which time the ADC may reliably perform analog-to-digital conversion.
FIG. 1 is a circuit diagram illustrating a known SH module. The module 100 includes a voltage source 110 with a resistor 120 in series (representing the source impedance, which, in general, can be a complex impedance having a reactive component), a SH circuit 130, and an ADC 140. SH circuit 130 includes a capacitor 134. The capacitor 134 may be referred to as a sampling capacitor or a hold capacitor.
A switch 132 switches the SH circuit 130 between three states: (1) the sampling state, when the switch 132 is coupled to the signal node A; (2) the holding state, when the switch 132 is in an open switch position, not shown in FIG. 1; and (3) a reset state, when the switch 132 couples the ADC 140 to a ground node (or in general to some reference node, particularly in the case of differential signals and circuits, when an explicit ground node is not used) to discharge the capacitor 134 and thus prepare the SH circuit 130 for a new sample.
The capacitor 134 obtains or acquires an analog input voltage provided at node A in the sampling state (also sometimes referred to as an acquisition state or a charging state) and stores this voltage during the holding state. The SH circuit 130 is a simplified representation of an SH circuit, allowing for easier description of the principle of operation. In practice, the SH circuit 130 may be more complex. For instance, the circuit 130 may have separate sample and hold (or load) capacitors. Often, such a circuit will have another capacitor used to transfer the charge from the sampling capacitor to the load capacitor. Such transfer is often accomplished by additional switches. During the holding state, the voltage on the capacitor settles (stabilizes) to a nearly constant value. Such a stable voltage signal may be processed by the ADC 140 and subsequent (downstream) system elements. The ADC 140 typically quantizes the signal to one of the 2N discrete values. N is the number of bits output from the ADC 140. The value of N thus determines the bit resolution. The quantization is followed by encoding of the quantized level into digital samples (or digital code or word). Often, ADCs have a built-in sample and hold function. Accordingly, the combination of SH 130 and ADC 140 is referred to as a sampling ADC, or simply an ADC.
FIG. 2 is a signal trace showing typical operation of the SH circuit 130. A prior art module such as the module 100 may be used to sample and hold a varying analog input voltage signal 205 at successive periods. An input voltage signal 205 that corresponds to a voltage at node A in FIG. 1, may vary over a specified dynamic range, e.g., between zero voltage and a full scale voltage FS. A “sampling period” begins at a time 210, with the objective of obtaining the voltage 240 of the input signal 205 corresponding to that time instant, and ends at a time 235. The sampling period comprises a sampling state, a holding state and a reset state. In the sampling state, SH circuit 130 charges. The sampling state (i.e. the charging of the capacitor 134) must be fast enough so that the input signal does not change significantly during the acquisition, otherwise a sampling error will occur.
Typically, the change in the input signal level is limited to less than 1 LSB. Upon completion of acquisition, the switch 132 opens and the capacitor 134 holds the charge in the holding state. During the holding state the voltage signal associated with the SH circuit 130 (and specifically the capacitor 134 therein) settles. As used herein, “settles” means stabilizes within predefined voltage levels or an associated tolerance. At point 230, the voltage 220 settles (e.g., remains stable to within one least significant bit (LSB) of the ADC). For example, if a 10-bit ADC having 210=1024 possible quantization values is used, the voltage will considered to have settled when the voltage remaining within 2−10 times the operating voltage range of the ADC (i.e., within a tolerance of +/−0.5*2−10*the operating range of the ADC with respect to the value that the input signal would settle given infinite time). When the voltage has settled, it may be suitable for digital conversion and encoding (i.e. for processing by downstream system components). At a time 235, the SH circuit 130 is reset by setting the switch 132 to the ground position. The voltage on the capacitor 134 may settle to zero before the next sampling period begins.
In FIG. 2, a sampling period T1 is shown, corresponding to a sampling frequency fs1 (i.e., T1=1/fs1). Thus, an input signal 205 is sampled periodically (e.g., at the points 270 and 272 spaced in time by T1). The combination of the sampling state and the holding state (e.g., between times 210 and 235) is referred to herein as an “attack”. The reset state (between times 235 and 250) is considered the “release”. The process repeats in the next sampling period, which starts at time 250, when the module 100 seeks to determine (sample and hold) the input voltage at point 272. The input voltage settles at a value 260 that is approximately equal to the level at the point 272. The digital conversion is then executed in the same manner as in the previous period described above.
Another known approach used to pre-process an analog signal for an ADC or other downstream system elements is known as track-and-hold (TH). Like an SH module 130, a TH module samples a signal by charging a capacitor. However, a TH module has only two states: (1) a tracking state, when the sampler is coupled to the signal and “follows” or tracks the signal; and (2) a holding state, when the sampler is disconnected from the signals and stores the charge making it available for digital conversion. The TH module does not switch to a reset state during each sampling period. Rather, the TH module transitions from a settled (held) sampled voltage level directly into attacking another sample.
One problem that results from the use of both SH and TH modules is that due to the time required for the voltage to settle, it takes a relatively long time to accurately capture the voltage level that the module desires to determine and digitize. The settling time can dominate the length of the sample period, putting a limit on the sample frequency. Accordingly, there is a need to shorten the sample period and thus increase the sample frequency.